1. Field of the Invention
The invention relates to an improved solid state logical current switch which is readily fabricated by large scale integration techniques. The improved integrated circuit logical current switch is particularly advantageously employed in high speed data processing systems and the like.
2. Description of the Prior Art
Numerous logical current switch circuits also termed "current mode switching circuits" or "emitter coupled logic circuits," are known to the art.
Current mode switching is well suited for high speed digital systems, for example, electronic computers and other electronic apparatus, since the transistors therein can be operated out of saturation with relatively small voltage swings, which may be in the order of a fraction of a volt. The avoidance of transistor saturation and the small voltage excursions enable current mode switching circuits to have a high speed of response.
One known type of current mode switching circuit includes at least two transistors having separate collector circuits and a common emitter circuit in which a current source is connected. The current source may be simulated by a source of operating potential and a common signal current path, such as a resistor. The current source current can be routed through either one of the alternate current paths provided by the collector to emitter paths of the transistors by application of a suitable difference in potential between the base electrodes thereof. When this type of current mode switching circuit is utilized as a logic gate, the difference in potential is achieved by applying relatively high (HI) and relatively low (LO) binary signal voltage levels to one transistor base electrode and a reference voltage (Vref) to the other transistor base electrode. A value intermediate to the HI and LO signal levels is assigned to Vref so that the potential difference between the two signal levels and Vref controls which of the transistors the current is routed through. This type of logic gate is commonly termed a current mode logic (CML) gate, a current switch logic (CSL) gate or an emitter coupled logic (ECL) gate.
In the usual type CML gate, complementary outputs are taken from the collector electrodes of the transistors. Each of the complementary outputs is often buffered by a separate emitter-follower (common collector) transistor. The dual emitter-follower transistors provide the CML gate with a low output impedance and provide signal level shift so that the output signal levels are of the same digital voltage levels as the binary input signals. Thus, the output terminals of one CML gate may be directly connected to the input terminals of not only one other CML gate, but also, due to the low output impedance, to the input terminals of several other CML gates.
Although the dual output emitter-follower transistors provide the afore mentioned benefits, they also account for about two-thirds of the power dissipation in the CML gate. Although power dissipation is generally undesirable, it is particularly so when the CML gates are fabricated as integrated circuits wherein the dissipated heat can cause serious performance degradation. The present invention is directed to novel improvements in CML gates whereby, among other advantages enumerated in detail hereinafter, the power dissipation is sizeably reduced without loss of signal gain and without loss of high performance.
Reference is made to U.S. Pat. No. 2,964,652, entitled "Transistor Switching Circuits" granted Dec. 13, 1960 to Hannon S. Yourke.
Reference is made to the description of Emitter Coupled Logic (ECL) pages 81- 82 of the text "Integrated Circuits" (Texas Instruments Electronic Series) by R. G. Hibberd, Copyright 1969, McGraw-hill Book Company.
Reference is made to U.S. Pat. No. 3,418,491 entitled "Utilizing Identical Signal Levels for Logic and Inhibit Functions" granted Dec. 24, 1968 to David H. Chung and James L. Walsh. U.S. Pat. No. 3,418,491 discloses a cascode amplifier circuit comprising two transistors, one transistor adapted to receive an input signal, and provide an output; the other transistor being adapted for constant voltage operation. An inhibit transistor, connected to the other transistor, is adapted to receive an input signal and provide an output. Identical signal levels operate the inhibit and one transistor. Operation of the one transistor renders the amplifier conductive. Simultaneous operation of the inhibit and one transistor terminates conduction through the amplifier. When the inhibit signal is dropped, no delay occurs at the amplifier output since no charge storage problems occur in the other transistor.
Reference is made to U.S. Pat. No. 3,458,719 entitled "Threshold Logic Switch With A Feedback-Current Path" granted July 29, 1969 to Leonard Weiss. The Weiss patent discloses an integrated circuit current switch having a time-dependent negative feed-back path for decreasing the switching time. The feed-back signal changes the level of the reference voltage applied to the current switch thereby decreasing the required level change in the potential of the input signal for the current switch to change its state.
Reference is made to U.S. Pat. No. 3,471,713 entitled "High-Speed Logic Module Having Parallel Inputs Direct Emitter Feed to A Coupling Stage and A Grounded Base Output," granted Oct. 7, 1969 to David C. Uimari. The Uimari patent discloses a gating circuit in which the emitter outputs from a plurality of parallel connected input transistors are fed to the base terminal of an intermediate or coupling stage transistor. The emitter output of the latter is directly connected to the emitter of a grounded base saturable output transistor in a current mode configuration, and the circuit output is taken from the collector of the output transistor.
Reference is made to U.S. Pat. No. 3,509,362 entitled "Switching Circuit" granted Apr. 28, 1970 to Frederick O. Bartholomew. The Bartholomew patent discloses signal translating means responsive to binary input signals to provide overdrive signals to a current mode switch. The signal translating means includes an inverting type amplifier with a gain G for inverting the binary signals and additionally includes means for applying the binary signals and the inverted binary signals to first and second current mode switch inputs, respectively, such that the differential signal swing between the current mode switch inputs is (1+G) multiplied by the binary input signal swing.
Reference is made to U.S. Pat. No. 3,521,086 entitled "Circuit Arrangement for Limiting the Output Voltage of a Logical Circuit" granted July 21, 1970 to Arie Slob. The Slob patent discloses a circuit arrangement for maintaining the output signal of an emitter coupled logic circuit at a non-varying value with respect to a voltage reference point in which the input logic element branches are connected to an output point through an amplifier. The output point is maintained at the non-varying value by being connected to the reference point through the base-emitter barrier layer of a transistor the collector of which is connected to the amplifier in negative feedback relationship.
Reference is made to U.S. Pat. No. 3,523,194 entitled "Current Mode Switch" granted Aug. 4, 1970 to Alfredo Sheng. The Sheng patent discloses current mode switching circuits having dual output emitter-follower output transistors. Power dissipation is reduced by switching a common load current path from one to the other output terminal as determined by the binary significance of the digital input signals, whereby the emitter current of only one of the emitter-follower transistors flows through the common path under steady state conditions.
Reference is made to U.S. Pat. No. 3,597,626 entitled "Threshold Logic Gate" granted Aug. 3, 1971 to John D. Heightley. The Heightley patent discloses a threshold logic gate comprising a threshold circuit and an input signal combining circuit including a non-linear impedance element. The non-linear impedance replaces the usual linear summing resistor in the input signal combining circuit and provides a low impedance below the gate threshold level and a high impedance in the gap. The low impedance below the gate threshold level permits a large fan in with a small overall signal swing on the threshold circuit, providing the gate with high speed operation and low power dissipation. At the same time the high impedance presented in the gap provides the gate with a large gap, thereby reducing the sensitivity requirements on the threshold circuit.
Reference is made to U.S. Pat. No. 3,751,680 entitled "Double-Clamped Schottky Transistor Logic Gate Circuit" granted Aug. 7, 1973 to David A. Hodges. The Hodges patent discloses a gate circuit having an output terminal switchable between two levels in response to a bilevel input signal on an input terminal. A totem pole output arrangement includes a pair of series connected Schottky clamped transistors, the first acting as a pull-up and the second a pull-down transistor. A common connection between the emitter and collector of the transistors provides the output terminal. A phase-splitting OR gate is provided for driving the base inputs of the transistors in a complementary manner. The OR gate has two activating inputs, the first being responsive to a high bi-level input signal for placing the pull-down transistor in conduction and holding off the pull-up transistor. The second input is responsive only during a low bi-level input signal to the first input. It receives a feedback signal from the output terminal for controlling the pull-up transistor to maintain the output terminal at a predetermined higher voltage level.
A number of logical circuit configurations requiring only a single supply source are known to the art. See, for example: U.S. Pat. No. 3,867,644 entitled "High Speed Low Power Schottky Integrated Logic Gate Circuit with Current Boost" granted Feb. 18, 1975 to Ronald L. Cline; U.S. Pat. No. 3,766,406, entitled "ECL to TTL Converter" granted Oct. 16, 1973 to Richard W. Bryant and Goerge K. Tu; U.S. Pat. No. 3,769,524, entitled "Transistor Switching Circuit" granted Oct. 30, 1973 to Keith F. Mathews; U.S. Pat. No. 3,836,789, entitled "Transistor-Transistor Logic Circuitry and Bias Circuit" granted Sept. 17, 1974 to James R. Struk and Robert G. Werner; and U.S. Pat. No. 3,783,308, entitled "Flip-Flop Element" granted Jan. 1, 1974 to Clark R. Williams.
Reference is made to the following IBM Technical Disclosure Bulletin publications:
No. 1: "Single Supply Current Switch" by E. Colao, Vol. 16, No. 12, May 1974, page 3937. A Schottky Barrier diode is connected from the base one transistor of the current switch to ground to provide the reference potential.
No. 2: "High-Speed, Diode-Transistor Current Switch" by T. S. Jen, Vol. 8, No. 8, January 1966, page 1150. A first transistor and a diode have their respective emitter and cathode connected through a resistor, to a source of potential, the common current switch configuration; the logical input is applied to the base of said first transistor. The collector potential of said first transistor and the anode potential of said diode are transmitted to the base inputs of a succeeding current switch which includes third and fourth transistors. The circuits complementary outputs are taken from the collectors of said third and fourth transistors.
No. 3: "Self-Biased, Low Voltage, Emitter-Followerless Current Switch" by R. J. Blumberg, J. A. Dorler and W. S. Homa. A plurality of input signals are received at the bases of a plurality of input switching transistors. The bias for the reference transistor is provided by a resistor network. A pair of Schottky diodes complete the internal biasing and regulation circuitry.
No. 4: "Schottky Diode Feedback Current-Switch Circuit" by K. F. Mathews, Vol. 15, No. 6, November 1972, page 1956. A Schottky Barrier diode shunts the collector base junction of each transistor employed.
No. 5: "Schottky Diode Current Switch" by J. W. Bode and K. F. Mathews, Vol. 14, No. 7, December 1971, page 2103. A Schottky Barrier diode is employed in place of the conventional diode 10 in the current switch, as shown in FIG. 1 of the Yourke U.S. Pat. No. 2,964,652.
No. 6: "Non Inverting High Threshold D.sup.2 L Circuit" by V. L. Gani and F. A. Montegari, Vol. 18, No. 8, January 1976, page 2503. The addition of a Schottky Barrier diode in the emitter circuit of the switching transistor provides a threshold 300 millivolts more positive than that of a standard D.sup.2 L circuit.
No. 7: "Active Terminator For Transmission Lines" by S. D. Malaviya and P. Smetana, Vol. 18, No. 5 October 1975, page 1417. The terminator circuitry disclosed includes first and second transistors each having a level shifting Schottky Barrier diode serially connected in its emitter circuit.